Truth table for a 4-input NAND gate is as given below:
A B C D F
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 1
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0
Simplifying K-map for the variable F,we get
F=A'+B'+C'+D'
=(A'+B')+(C'+D')
Using De-Morgan's theorem,we get
=(AB)'+(CD)'
The NAND circuit for this logic can be represented as:
A B C D F
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 1
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0
Simplifying K-map for the variable F,we get
F=A'+B'+C'+D'
=(A'+B')+(C'+D')
Using De-Morgan's theorem,we get
=(AB)'+(CD)'
The NAND circuit for this logic can be represented as:
4-input NAND GATE implementation using 2-input NAND GATES |
Draw the Synchronous Moore FSM for detecting the non-overlapping 1011 pattern.
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