FULL ADDER design using lesser number of gates

Truth table for a full adder:
A       B       Cin      C       S
0        0         0        0       0
0        0         1        0       1
0        1         0        0       1
0        1         1        1       0
1        0         0        0       1
1        0         1        1       0
1        1         0        1       0
1        1         1        1       1

Generally,
S=A xor B xor Cin
Cout=AB+BCin+ACin
needs:
2 2 i/p xor gates
3 2 i/p and gates
1 3-i/p or gate

Another method
S=A xor B xor Cin
Lets solve the K-map for C differently

C=AB+Cin(A xor B)
needs
2 2 i/p xor gates
2 2 i/p and gates
1 2 i/p or gate

Since prop delay through any gate depends on :
type of gate , no.of i/p
therefore 2nd design may prove to be beneficial in some cases.