The BIG Q - Why motor is configured to run in delta connection and not in star??

You must have observed that there is a rating mentioned on every motor like....some...KW

Whenever a motor is connected in delta, it offers a power equal to this rating.

Whereas, when the motor windings are connected in star, the power offered is much less than this rating.

Power=(KW rating)/3

Also, you know that torque is proportional to power.

So, in order to use a motor optimally, we connect the windings in delta.

However, there is a large amount of current when the motor starts, so in order to keep these windings from burning out, it is preferred that initially the motor should be star configured( current divides in star configuration,right!) and after gaining momentum, it should switch to delta configuration.

P.S:

It is not mandatory to use delta configuration in motor. Star configuration can also be used, but the problem is that you'll not like a motor that runs slow and stops or burns it's windings whenever a heavy load is encountered, right??

Hence, star configuration loses the race with delta configured motor in terms of the power offered, torque, speed and the heavy load handling capacity of these two.

FULL ADDER design using lesser number of gates

Truth table for a full adder:
A       B       Cin      C       S
0        0         0        0       0
0        0         1        0       1
0        1         0        0       1
0        1         1        1       0
1        0         0        0       1
1        0         1        1       0
1        1         0        1       0
1        1         1        1       1

Generally,
S=A xor B xor Cin
Cout=AB+BCin+ACin
needs:
2 2 i/p xor gates
3 2 i/p and gates
1 3-i/p or gate

Another method
S=A xor B xor Cin
Lets solve the K-map for C differently

C=AB+Cin(A xor B)
needs
2 2 i/p xor gates
2 2 i/p and gates
1 2 i/p or gate

Since prop delay through any gate depends on :
type of gate , no.of i/p
therefore 2nd design may prove to be beneficial in some cases.

4-input NAND gate using 2-input NAND gates

Truth table for a 4-input NAND gate is as given below:

A       B       C       D        F
0        0        0       0        1
0        0        0       1        1
0        0        1       0        1
0        0        1       1        1
0        1        0       0        1
0        1        0       1        1
0        1        1       0        1
0        1        1       1        1
1        0        0       0        1
1        0        0       1        1
1        0        1       0        1
1        0        1       1        1
1        1        0       0        1
1        1        0       1        1
1        1        1       0        1
1        1        1       1        0


Simplifying K-map for the variable F,we get
F=A'+B'+C'+D'
=(A'+B')+(C'+D')
Using De-Morgan's theorem,we get
=(AB)'+(CD)'

The NAND circuit for this logic can be represented as:

4-input NAND GATE implementation using 2-input NAND GATES

MINTERM ,CANONICAL SUM OF PRODUCTS(SOP) and MINIMUM SOP

MINTERM:
A minterm is a product term that contains all the variables of a logical function either in true or inverted state.

A logical function is given:
F=AB'+C'

Its truth table is as below:

A  B C F
0 0         0        1
0 0 1        0
0 1         0        1
0 1         1        0
1 0         0        1
1 0         1        1
1 1         0       1
1 1        1        0

All the minterms that can be generated from the above given truth table are:

A'B'C' , A'B'C , A'BC' , A'BC , AB'C' , AB'C , ABC' , ABC

CANONICAL SOP:
It is an expression that describes a logical function from its truth table.A canonical SOP consists of the sum of all the minterms for which the function has a value 1...or the function is true.

For the same truth table as stated above ,the canonical SOP can be written as:
F=A'B'C'+A'BC'+AB'C'+AB'C+ABC'

MINIMUM SOP:
A minimum minterm is obtained by simplifying a canonical SOP. It provides a minimum hardware simplification of the logic function.
For the same truth table,the minimum SOP obtained after simplification is:

F=AB'+C'

"AND", "OR", "NOT" IMPLEMENTATION USING "NOR" GATE

Conversion of a NOR gate into a NOT gate, an OR gate and an AND gate is as shown below:

NOR IMPLEMENTATION

"AND", "OR", "NOT" IMPLEMENTATION USING "NAND" GATE

Conversion of a NAND gate into an AND gate ,a NOT gate and an OR gate is as shown below:

NAND IMPLEMENTATION

UNIVERSAL GATES

NAND and NOR are the universal gates.
AND , OR and NOT are fundamental gates,together they can  implement any digital logic.But NAND or NOR alone is capable enough to implement any digital logic,hence these two gates are called universal Gates.